1. Field of the Invention
The present invention generally relates to semiconductor defect monitors which enable defect distribution density to be determined for various sizes of defects, and more specifically, to a defect monitoring structure which permits testing for all defects in a semiconductor wafer without interference between adjacent patterns and different defect-monitoring tests.
2. Description of the Prior Art
In the development of integrated circuitry, and particularly large scale integrated circuits (LSI), design philosophy has become more concerned with the economics of total performance of the circuits rather than individual device parameters within the circuit. This is due in part to the fact that integrated circuits involve such a complicated pattern or interconnection of a multiplicity of components that the individual components cannot be readily isolated for testing purposes. In the past, special test sites have been formed at certain locations on the semi-conductor wafer, but the information afforded by various measurements made at these special test sites has been insufficient to predict the t.sub.0 -yield and reliability of the product integrated circuits formed concurrently with the test sites on the wafer.